1. FIELD OF THE INVENTION
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of forming a halo implant in a substrate adjacent one side of a structure such as a gate structure of a transistor.
2. DESCRIPTION OF THE RELATED ART
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the channel length of a transistor also increases xe2x80x9cshort-channelxe2x80x9d effects, almost by definition. Short-channel effects include, among other things, an increased drain-source leakage current when the transistor is supposed to be switched xe2x80x9coff,xe2x80x9d due to source/drain depletion regions being closer together because of the shorter channel length. Short-channel effects also include xe2x80x9cthreshold roll-offxe2x80x9d (i.e., the threshold voltage Vth decreasing as gate length is reduced), and the like.
Short-channel effects may be reduced by using angled halo implants. Angled halo implants are implants of dopants that effectively xe2x80x9creinforcexe2x80x9d the doping type of the substrate in the channel between the source/drain extension (SDE) regions (formerly known as lightly doped drain or LDD regions). For example, for an N-MOS transistor, the doping type of the substrate in the channel between the n-type source/drain extension (SDE) regions is p-type. The angled halo implant may be boron (B) or boron difluoride (BF2) implanted into the substrate at an angle (with respect to a direction perpendicular to the surface of the substrate), and with a dose that may range from about 1.0xc3x971012-1.0xc3x971014 ions/cm2 at an implant energy ranging from about 5-15 keV for B and about 20-70 keV for BF2.
Similarly, for a P-MOS transistor, the doping type of the substrate in the channel between the p-type source/drain extension (SDE) regions is n-type. The angled halo implant may be arsenic (As) implanted into the substrate at an angle (with respect to a direction perpendicular to the surface of the substrate), and with a dose that may range from about 1.0xc3x971012-1.0xc3x971014 ions/cm2 at an implant energy ranging from about 40-70 keV for As.
As shown in FIG. 1, for example, a metal oxide semiconductor field effect transistor (MOSFET or MOS transistor) 100 may be formed on a semiconducting substrate 105, such as doped-silicon. The MOS transistor 100 may have a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate 110 formed above a gate oxide 115 formed above the semiconducting substrate 105. The doped-poly gate 110 and the gate oxide 115 may be separated from N+-doped (P+-doped) source/drain regions 120 of the MOS transistor 100 by dielectric spacers 125. The dielectric spacers 125 may be formed above shallow N-doped (P-doped) source/drain extension (SDE) regions 130.
As shown in FIG. 1, Pxe2x88x92-doped (Nxe2x88x92-doped) angled halo implants 135 are typically provided adjacent the N-doped (P-doped) SDE regions 130 to reduce some of the short-channel effects described above. In particular, by xe2x80x9creinforcingxe2x80x9d the p-doping (n-doping) type of the semiconducting substrate 105 in the channel between the N-doped (P-doped) SDE regions 130, the laterally non-uniform Pxe2x88x92-doped (Nxe2x88x92-doped) angled halo implants 135 may be better at controlling the threshold roll-off (i.e., the threshold voltage Vth decreasing as gate length is reduced), thereby reducing short-channel induced effects such as a non-zero drain-source leakage current when the transistor is supposed to be switched xe2x80x9coff,xe2x80x9d (i.e., xe2x80x9coff-statexe2x80x9d leakage). As shown in FIG. 1, shallow trench isolation (STI) regions 140 may be provided to isolate the MOS transistor 100 electrically from neighboring semiconductor devices such as other MOS transistors (not shown).
As shown in FIG. 2, only one Pxe2x88x92-doped (Nxe2x88x92-doped) angled halo implant 235 typically needs to be provided adjacent the N-doped (P-doped) SDE region 230 adjacent the N+-doped (P+-doped) source region 220 of the MOS transistor 200 to reduce some of the short-channel effects described above. Note that elements of the MOS transistor 200 that are substantially identical to the elements of the MOS transistor 100 as shown in FIG. 1 are numbered identically.
As shown in FIG. 3, a conventional technique for implanting the asymmetric Pxe2x88x92-doped (Nxe2x88x92-doped) angled halo implant 235 is schematically illustrated. A structure 300 (that will eventually become a gate structure for an MOS transistor such as the MOS transistor 200, as described above), having a doped-poly gate 110 and a gate dielectric 115, may be masked by a mask 310. The mask 310 may be formed of photoresist, for example, and may have a thickness in a range of about 5000 xc3x8515000 xc3x85.
As shown in FIG. 3, a halo dopant 320 (indicated by directed lines) may be implanted to introduce dopant atoms and/or molecules to form the asymmetric Pxe2x88x92-doped (Nxe2x88x92-doped) angled halo implant 235 only under the lefthand side of the structure 300. As shown in FIG. 3, an angle xcex8 of the halo dopant 320 with respect to an upper surface 145 of the semiconducting substrate 105 may lie within a range of about 25xc2x0-65xc2x0.
Typically, the semiconducting substrate 105 is tilted at the angle xcex8 with respect to a horizontal direction in an implanter (not shown) and the halo dopant 320 is directed downward in a vertical direction. Alternatively, the semiconducting substrate 105 could be disposed in the horizontal direction in the implanter (not shown) and the halo dopant 320 could be directed downward at the angle xcex8 with respect to the horizontal direction in the implanter, and/or any other combination of tilt and implant direction could be used as long as the angle xcex8 is the relative angle of the halo dopant 320 with respect to the upper surface 145 of the semiconducting substrate 105.
After implanting one side of the structure 300, the semiconducting substrate 105 is typically rotated through 180xc2x0 and the halo dopant 320 is again implanted so that the angle xcex8 is the relative angle of the halo dopant 320 with respect to the upper surface 145 of the semiconducting substrate 105. If the mask 310 were not present, such symmetrical implanting of both sides of the structure 300 would result in symmetrical angled halo implants similar to the angled halo implants 135 shown in FIG. 1. With the mask 310 present, however, symmetrical implanting of both sides of the structure 300 results in an asymmetrical angled halo implant similar to the asymmetrical angled halo implant 235 shown in FIGS. 2 and 3.
The halo dopant 320 may also be implanted into a region 330 (outlined in phantom) that will eventually become the N-doped (P-doped) SDE region 230, and into a region 320 (also outlined in phantom) that will eventually become the N+-doped (P+-doped) source region 220. However, the dosage of the halo dopant 320 is typically at least an order of magnitude less than the dosage of dopant for the N-doped (P-doped) SDE region 230. Similarly, the halo dopant 320 may also be implanted into the doped-poly gate 110 and/or the gate dielectric 115 and/or the mask 310. However, the doping of the doped-poly gate 110 also typically overwhelms the halo dopant 320 doping in the doped-poly gate 110. Furthermore, the amount of the halo dopant 320 doping in the gate dielectric 115 is typically miniscule, and the mask 310 is ultimately removed, rendering moot the presence of any of halo dopant 320 doping in the mask 310.
Typically, a dose of the halo dopant 320 atoms and/or molecules may range from approximately 1.0xc3x971012-1.0xc3x971014 ions/cm2 of the appropriate halo dopant 320 atoms and/or molecules, e.g., boron (B) or boron difluoride (BF2) for an illustrative NMOS transistor (the p-type halo implant serving to reinforce the p-type doping of the channel region of the NMOS transistor), or arsenic (As) or phosphorus (P) for an illustrative PMOS transistor (the n-type halo implant serving to reinforce the n-type doping of the channel region of the PMOS transistor). An implant energy of the halo dopant 320 atoms and/or molecules may range from approximately 5-70 keV.
By way of contrast, a typical dose of dopant for the N-doped (P-doped) SDE region 230 may range from approximately 1.0xc3x971014-1.0xc3x971015 ions/cm2 of the appropriate dopant atoms and/or molecules, e.g., As or P for an illustrative NMOS transistor or B or BF2 for an illustrative PMOS transistor. An implant energy of the N-doped (P-doped) SDE region 230 dopant atoms and/or molecules may range from approximately 3-50 keV. Similarly, a typical dose of dopant for the N+-doped (P+-doped) source region 220 may range from approximately 1.0xc3x971015-1.0xc3x971015 ions/cm2 of the appropriate dopant atoms and/or molecules, e.g., As or P for an illustrative NMOS transistor or B or BF2 for an illustrative PMOS transistor. An implant energy of the N+-doped (P+-doped) source region 220 dopant atoms and/or molecules may range from approximately 30-100 keV.
The halo dopant 320 may be an Nxe2x88x92 implant such as P, As, antimony (Sb), and the like, and will form the Nxe2x88x92-doped angled halo implant 235. An Nxe2x88x92 implant would be appropriate for the fabrication of a PMOS transistor 200, for example, the n-type halo implant serving to reinforce the n-type doping of the channel region of the PMOS transistor 200. Alternatively, the halo dopant 320 may be a Pxe2x88x92 implant such as B, boron fluoride (BF, BF2), Indium (In), and the like, and may form the Pxe2x88x92-doped angled halo implant 235. A Pxe2x88x92 implant would be appropriate for the fabrication of an NMOS transistor 200, for example, the p-type halo implant serving to reinforce the p-type doping of the channel region of the NMOS transistor 200.
However, the conventional technique schematically illustrated in FIG. 3 for implanting the asymmetric Pxe2x88x92-doped (Nxe2x88x92-doped) angled halo implant 235 necessarily entails an extra masking step to form the mask 310, adding yet another layer of complexity, increasing further the costs of fabrication and reducing throughput. Alternative conventional techniques for implanting the asymmetric Pxe2x88x92-doped (Nxe2x88x92-doped) angled halo implant 235, as shown in FIG. 4, impose severe restrictions on the design and layout of the MOS transistors on a workpiece (such as the semiconducting substrate 105 in FIG. 3) so that all of the N+-doped (P+-doped) source regions 220 are on the same side of the gate structures (such as structure 300 in FIG. 3).
As shown in FIG. 4, these alternative conventional techniques then use LDD or SDE mask(s) as mask(s) 410 to form the asymmetric Pxe2x88x92-doped (Nxe2x88x92-doped) angled halo implant 235. The LDD or SDE mask(s) 410 are used in conventional complementary MOS (CMOS) fabrication methods to protect the PMOS (NMOS) transistor regions while the NMOS (PMOS) transistor regions are being implanted to form the N-doped (P-doped) SDE regions 330 and 430 (outlined in phantom), for example. In addition to forming the asymmetric Pxe2x88x92-doped (Nxe2x88x92-doped) angled halo implant 235, the halo dopant 320 may also be implanted into a region 430 (outlined in phantom) that will eventually become the N-doped (P-doped) SDE region 130, forming an asymmetric Pxe2x88x92-doped (Nxe2x88x92-doped) angled halo implant 435 under one side of the mask(s) 410, for example. The angled halo dopant 320 is thus only implanted under one side of the gate structure(s) 300, the side having the region 320 (also outlined in phantom) that will eventually become the N+-doped (P+-doped) source region 220. However, the severe design and layout restrictions result in a sparser and less dense packing of the CMOS transistors on the workpiece and the addition of yet another layer of design and layout complexity, increasing the costs of fabrication and also reducing overall throughput.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided for forming a halo implant in a substrate adjacent one side of a structure, the method including forming the structure above a surface of the substrate, the structure having first and second edges and forming a mask defining a region adjacent the structure, the mask having a thickness xcfx84 above the surface and having an edge disposed a distance xcex4 from the first edge of the structure. The method also includes implanting the halo implant at an angle xcex1 with respect to a direction perpendicular to the surface, wherein the tangent of the angle xcex1 is at least the ratio of the distance xcex4 to the thickness xcfx84.